1. Field of the Invention.
The present invention relates to a picture enhancing circuit for use with digital video tape recorders (VTR's).
2l . Description of the Prior Art.
Editing on digital VTR's often involves varying the playback speed and can involve playing back the tape at a speed higher than normal reproduction speed. In such a variable speed reproduction mode, the magnetic head of the machine does not follow the path of the originally recorded diagonal tracks on the tape but, as shown by the broken line in FIG. 8 of the accompanying drawings, runs across the tracks (shown in solid line).
Thus under the variable speed reproduction mode, recorded data on the tape is reproduced from a plurality of tracks thereof depending on the actual speed. Suppose that a magnetic head 3 attached to a rotating drum 2 is used to record and reproduce signals as shown in FIG. 9 and that a plurality of sync blocks constitute a one-track field signal as depicted in FIG. 10. During playback the reproduced field signal is written to a field memory or the like in units of sync blocks and a single picture is produced by reading the sync blocks one-by-one from the field memory.
The data written to the field memory is held unchanged unless and until new data is written thereto. If the field signal reproduced by the magnetic head 3 has a corresponding reproduced sync block, the whole corresponding sync block is replaced by the new sync block. However where the playback speed is varied from the normal speed, not all of the recorded data is reproduced and so some data in the field memory will not be updated. It follows that where the data of the same sync block in successive pictures is not encountered for a certain period of time because of the varying speed of reproduction, the picture data of the old sync block is used as the reproduced picture signal. This means that mutually uncorrelated items of data will be utilized to construct the reproduced picture. This can result in reproduced pictures being poorly animated or appearing dragged across the screen, thereby drastically deteriorating the quality and degree of recognition of reproduced pictures.
The degraded correlation between data items may be somewhat alleviated by using interpolation depending on whether the sync block data about to be used is new or old as proposed by the present assignee in U.S. Pat. No. 4,799,113. The alleviated correlation enhances the degree of reproduced picture quality.
FIG. 11 is a block diagram of the prior art picture enhancing circuit. The enhancing circuit of FIG. 11 comprises a single reproduction system that uses a pair of reproducing magnetic heads shown in FIG. 9. In FIG. 11, a reproduced field signal input through a terminal 11 is sent to a sync detection circuit 12 and an error correction circuit 13 (e.g. an inner code corrector). The sync detection circuit 12 detects sync data inserted in each sync block. The detected sync data is used by the error correction circuit 13 to correct the reproduced field signal.
If the sync data has no error or if the error found therein is of a correctable nature, ID information inserted in the sync block is relied on to write to a field memory 14 the picture data from that sync block.
The picture data read from the field memory 14 is fed to an interpolation circuit 15. Interpolation is carried out only when the interpolation conditions, to be described later, are met where the picture data of an old sync block is used. Otherwise the picture data is allowed to pass through the field interpolation circuit 15 unprocessed. The reproduced output interpolated or passed on unprocessed appears at a terminal 16.
A sync flag memory 17 has as many memory areas as the sync blocks of a field. When picture data is written to the field memory 14, a sync flag, e.g. of eight bits, is written to the memory area corresponding to the sync block of the picture data or more specifically the contents of the sync flag in the applicable area are reset e.g. to zero.
When the picture data of the corresponding sync block is read from the field memory 14, the sync flag is also read from the sync flag memory 17 synchronously with the picture data read operation. The flag is incremented by 1 by an incrementer 18, and then the flag is rewritten to the same sync block memory area.
For example, if the picture data of a sync block i is read from the field memory 14, the corresponding sync flag (see FIG. 12) is incremented by 1. The updated sync flag is written to the same sync block memory area i, as shown in FIG. 13. As mentioned when new picture data is written to the field memory 14, the corresponding sync flag is reset accordingly which causes the whole contents of the sync flag to be reset to 0, as depicted in FIG. 12.
The sync flag read from the memory 17 is passed on to a flag decoder 19 for determination of the flag value. If the flag value is found to exceed a predetermined reference value (e.g., 30-50), indicating that it is very old data which has been used several times and not overwritten by new data, a "1" is output by the flag decoder 19, which triggers interpolation. This is because picture data which is too old, if used unchecked, loses its correlation to other picture data and hence lowers the degree of recognition of reproduced pictures.
The foregoing description applies to digital VTR's having a single reproduction system. If two reproduction systems are incorporated as shown in FIG. 14, the newer of the two streams of picture data reproduced therefrom may be selected for picture reproduction. This scheme enhances the degree of reproduced picture recognition appreciably.
As shown in FIG. 14 this magnetic head device has four recording magnetic heads 3 and also two independently provided reproduction systems. That is, four magnetic heads make up a first reproduction system 4, close to which is located a separate second reproduction system 5.
FIG. 15 is a block diagram of a prior art picture enhancing circuit 10 that utilizes the rotating magnetic head device of FIG. 14. As shown in FIG. 15, the picture recognition enhancing circuit 10 comprises first and second enhancing circuits 10A and 10B each of which has a basic construction the same as that in FIG. 11. In this example, the reproduced outputs from the first and second reproduction systems 4 and 5 enter terminals 11 and 21, respectively. From the terminals, the reproduced outputs are written to field memories 14 and 24 in units of sync blocks, the picture data in the outputs being later read therefrom in the same units. When read from the field memories 14, 24, the picture data is supplied to a changeover switch 31 for selection of the most recent picture data within the same sync block. The picture data thus selected serves as the data for picture reproduction.
The changeover switch 31 works as follows: The sync flag of the same sync block from the sync flag memories 17 and 27 are fed to a flag comparator 32 and a flag decoder 33. The flag comparator detects the sync flag having the smaller of the two values (the detected flag indicates the sync block containing the most recent picture data). The detected flag activates the changeover switch 31 so as to select the most recent picture data from among the picture data coming from the field memories 14 and 24.
The flag decoder 33 compares the sync flag value selected on the basis of the detected flag with the above-mentioned reference value. If the detected flag is found to exceed the reference value, the interpolation circuit 15 is activated to interpolate the picture data.
The system of FIG. 15, which reproduces pictures always on the basis of the most recent picture data, provides a more enhanced degree of reproduced picture recognition than the constitution of FIG. 11.
However, these prior art setups have a major disadvantage. The system of FIG. 11 requires the memory 17 in which to retain sync flags, while that of FIG. 15 needs two such memories. Although these memories 17 and 27 are required to have only limited amounts of memory capacity, the comparable small-capacity memories are difficult to procure on today's memory market. Manufacturers are thus forced to utilize commercially available memories that have a far greater capacity than is actually needed which is a significant waste of resources.